Verilog Code of Decoder | 3 to 8 Decoder Verilog Code

Verilog Code of Decoder

3 to 8 Decoder Verilog Code

In this post we are going to share with you the verilog code of decoder. As you know, a decoder asserts its output line based on the input. For a 3 : 8 decoder, total number of input  lines is 3 and total  number of output lines is 8. Based on the input, only one output line will be at logic high.

The verilog code for 3:8 decoder with enable logic is given below.

3:8 Decoder Verilog Code

 

The Test bench for 3:8 Decoder is given below.

3:8 Decoder Test Bench

 

The output is is given below.

decoder simulation

 

If you have any query/suggestion please feel free to comment below the post.

 

 

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Nithin
Nithin
1 month ago

Is there any alternative code

Sin
Sin
1 month ago
Reply to  Nithin

Yes there is 3 types of modelling in vhdl program

Sin
Sin
1 month ago
Reply to  Sin

Namely 1.structural
2.dataflow level
3.behavioural
To write the program (・∀・)