4:1 Mux using 2:1 Mux Verilog Code and Explanation

This guide demonstrates how to implement a 4:1 multiplexer using only 2:1 multiplexers in Verilog.

Logic Overview

A 4:1 Mux can be built by cascading three 2:1 Muxes. Two 2:1 Muxes handle the first level of selection, and a third makes the final choice.

Verilog Code

module mux_2to1 (input I0, input I1, input S, output Y);
  assign Y = S ? I1 : I0;
endmodule

module mux_4to1_using_2to1 (input I0, input I1, input I2, input I3, input S1, input S0, output Y);
  wire mux1_out, mux2_out;

  mux_2to1 mux1 (
    .I0(I0),
    .I1(I1),
    .S(S0),
    .Y(mux1_out)
  );

  mux_2to1 mux2 (
    .I0(I2),
    .I1(I3),
    .S(S0),
    .Y(mux2_out)
  );

  mux_2to1 mux3 (
    .I0(mux1_out),
    .I1(mux2_out),
    .S(S1),
    .Y(Y)
  );
endmodule
    

Code Working

The mux_2to1 module is a basic 2:1 multiplexer. The mux_4to1_using_2to1 module uses three mux_2to1 modules to implement the 4:1 multiplexer. S0 and S1 are the select lines.