4-Bit Ripple Carry Adder: Verilog Implementation

This guide presents a Verilog implementation of a 4-bit ripple carry adder using full adder modules. Essential code and explanations are provided.

Full Adder Module

The fundamental building block is the full adder.

module full_adder (input a, input b, input cin, output sum, output cout);
  assign sum = a ^ b ^ cin;
  assign cout = (a & b) | (cin & a) | (cin & b);
endmodule
    

4-Bit Ripple Carry Adder

The 4-bit adder is constructed by cascading four full adders.

module ripple_carry_adder_4bit (input [3:0] A, input [3:0] B, input cin, output [4:0] Sum);
  wire c1, c2, c3;

  full_adder FA0 (A[0], B[0], cin, Sum[0], c1);
  full_adder FA1 (A[1], B[1], c1, Sum[1], c2);
  full_adder FA2 (A[2], B[2], c2, Sum[2], c3);
  full_adder FA3 (A[3], B[3], c3, Sum[3], Sum[4]);
endmodule
    

Explanation

Carry-out from each full adder stage is connected to the carry-in of the subsequent stage. The final carry-out is represented by Sum[4].