Carry Select Adder Verilog Code | 16 bit Carry Select Adder Verilog Implementation

Carry Select Adder Verilog Code

Verilog Implementation of  Carry Select Adder

A carry select adder is a particular way to implement an adder, which is a logic element that computes the (n+1)-bit sum of two n-bit numbers. The carry select adder is simple but rather fast. For more information about carry select adder you can refer to this wikipedia article. Also,  you can go through  Ripple Carry Adder, Carry Skip AdderCarry Look-ahead Adder etc. posts to get insight about different adders.

Basic structure of 4-bit Carry Select Adder is shown below.

 

carry select adder 4 bit

 

The Verilog Code for 16-bit  Carry Select Adder is given below-

 

Carry Select  Adder Simulation Result is as follows:

Carry Select Simulation
16 bit Carry Select Adder Testbench

 

Cadence RTL compiler is used to synthesize the verilog  code with Uofu standard library.  We got the following schematic after mapping the hdl code to the standard library. This is basically the synthesized view.

16 bit Carry Select Adder Module:

 

4 bit Carry Select Adder Module:

 

If you have any query/suggestion please feel free to comment below the post.

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fzh
fzh
2 years ago

plz write testbench

abc
abc
8 months ago

you did not use the half adder module in anything

Admin
Admin
7 months ago
Reply to  abc

It’s used in full adder module.