8-Bit Carry Select Adder: Verilog with 4-Bit Ripple Adders

This guide presents an 8-bit carry select adder implemented in Verilog, utilizing 4-bit ripple carry adder modules.

4-Bit Ripple Adder (Base Module)

module ripple_carry_adder_4bit (input [3:0] A, input [3:0] B, input cin, output [4:0] Sum);
  wire c1, c2, c3;

  full_adder FA0 (A[0], B[0], cin, Sum[0], c1);
  full_adder FA1 (A[1], B[1], c1, Sum[1], c2);
  full_adder FA2 (A[2], B[2], c2, Sum[2], c3);
  full_adder FA3 (A[3], B[3], c3, Sum[3], Sum[4]);
endmodule

module full_adder (input a, input b, input cin, output sum, output cout);
  assign sum = a ^ b ^ cin;
  assign cout = (a & b) | (cin & a) | (cin & b);
endmodule
    

8-Bit Carry Select Adder

module carry_select_adder_8bit (input [7:0] A, input [7:0] B, input cin, output [8:0] Sum);
  wire c4;
  wire [4:0] Sum_0, Sum_1;

  ripple_carry_adder_4bit lower_adder (A[3:0], B[3:0], cin, Sum[3:0], c4);
  ripple_carry_adder_4bit upper_adder_0 (A[7:4], B[7:4], 1'b0, Sum_0[3:0], Sum_0[4]);
  ripple_carry_adder_4bit upper_adder_1 (A[7:4], B[7:4], 1'b1, Sum_1[3:0], Sum_1[4]);

  assign Sum[7:4] = c4 ? Sum_1[3:0] : Sum_0[3:0];
  assign Sum[8] = c4 ? Sum_1[4] : Sum_0[4];
  assign Sum[3:0] = Sum[3:0];
endmodule

Explanation

The lower 4 bits are computed using a standard 4-bit ripple carry adder. The upper 4 bits are computed twice, once with carry-in 0 and once with carry-in 1. The carry-out from the lower 4 bits (c4) selects the correct upper 4 bits and the final carry-out.