Full Adder Verilog Code
Verilog Code of Full Adder
In this post we are going to share with you the Full Adder Verilog Code using two Half Adders.
The Verilog code of full adder using two half adder and one or gate is shown below.
////////////////////////////////////////// //1bit Full Adder ///////////////////////////////////////// module full_adder(a,b,cin,sum, cout); input a,b,cin; output sum, cout; wire x,y,z; half_adder h1(.a(a), .b(b), .sum(x), .cout(y)); half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z)); or or_1(cout,z,y); endmodule //////////////////////////////////////////////// // 1 bit Half Adder ///////////////////////////////////////////////// module half_adder( a,b, sum, cout ); input a,b; output sum, cout; xor xor_1 (sum,a,b); and and_1 (cout,a,b); endmodule
In above code we used gate level modeling along with instantiation. The above full adder code can be written in data flow model as shown below.
////////////////////////////////////////////////////////////// //1bit Full Adder ///////////////////////////////////////////////////////////// module full_adder(a,b,cin,sum, cout); input a,b,cin; output sum, cout; wire x,y,z; half_adder h1(.a(a), .b(b), .sum(x), .cout(y)); half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z)); assign cout= y|z; endmodule //////////////////////////////////////////////////// // 1 bit Half Adder ///////////////////////////////////////////////////// module half_adder( a,b, sum, cout ); input a,b; output sum, cout; assign sum= a^b; assign cout= a & b; endmodule
Full Adder Simulation Result:
