4:1 MUX Verilog Code | 2:1 MUX Verilog Code | Multiplexer Verilog Code

 

2:1 MUX Verilog Code

4:1 MUX Verilog Code

Multiplexer Verilog Code

 

In this post we are sharing with you the verilog code of different multiplexers such as 2:1 MUX, 4:1 MUX etc.

I am sure you are aware of  with working of a Multiplexer. The general block level diagram of a Multiplexer is shown below.

mux

When sel is at logic 0 out=I0 and when select is at logic 1 out=I1.

2:1 MUX Verilog in Data Flow Model is given below.

 

Verilog Code of 2:1 MUX in Behavioral Model is given below.

 

Simulation Result:

2X1 Mux Simulation

 

Now we are going to share with you the 4:1 MUX verilog code in dataflow and behavioral.

4:1 MUX Verilog Code in Dataflow model is given below.

 

4:1 MUX Verilog Code in Behavioral model is given below.

Simulation Result:

 

4X1 MUX Verilog Code

 

If you have any query/suggestion please feel free to comment below the post.

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