16 bit Radix 4 Booth Multiplier Verilog Code
Here we are sharing the verilog implementation of 16 bit radix 4 booth multiplier using sequential logic. It takes 16 clock cycle to multiply two 16-bit signed numbers.
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//Booth Multiplier 16-bit module multiplier ( input clk,reset, input [15:0] x,y, output reg [31:0] out ); reg [2:0] c=0 ; reg [31:0] pp=0; //partial products reg [31:0] spp=0; //shifted partial products reg [31:0] prod=0; reg [15:0] i=0,j=0; reg flag=0, temp=0 ; wire [15:0] inv_x ; //assign x= (~x) +1'b1; assign inv_x = (~x) +1'b1; always@(posedge clk) begin if(reset) begin out=0; c=0; pp=0; flag=0; spp=0; i=0; j=0; prod=0; end else begin if(!flag) c={y[1],y[0],1'b0}; flag=1; case(c) //////////////////////// 3'b000,3'b111: begin if(i<8) begin i=i+1; c={y[2*i+1],y[2*i],y[2*i-1]}; end else c=3'bxxx; end //////////////////////////// 3'b001,3'b010: begin if(i<8) begin i=i+1; c={y[2*i+1],y[2*i],y[2*i-1]}; pp={{16{x[15]}},x}; if(i==1'b1) prod=pp; else begin temp=pp[31]; j=i-1; j=j<<1; spp=pp<<j; spp={temp,spp[30:0]}; prod=prod+spp; end end else c=3'bxxx; end /////////////////////////// 3'b011: begin if(i<8) begin i=i+1; c={y[2*i+1],y[2*i],y[2*i-1]}; pp={{15{x[15]}},x,1'b0}; if(i==1'b1) prod=pp; else begin temp=pp[31]; j=i-1; j=j<<1; spp=pp<<j; spp={temp,spp[30:0]}; prod=prod+spp; end end else c=3'bxxx; end /////////////////////////// 3'b100: begin if(i<8) begin i=i+1; c={y[2*i+1],y[2*i],y[2*i-1]}; pp={{15{inv_x[15]}},inv_x,1'b0}; if(i==1'b1) prod=pp; else begin temp=pp[31]; j=i-1; j=j<<1; spp=pp<<j; spp={temp,spp[30:0]}; prod=prod+spp; end end else c=3'bxxx; end //////////////////////////////////// 3'b101, 3'b110: begin if(i<8) begin i=i+1; c={y[2*i+1],y[2*i],y[2*i-1]}; pp={{16{inv_x[15]}},inv_x}; if(i==1'b1) prod=pp; else begin temp=pp[31]; j=i-1; j=j<<1; spp=pp<<j; spp={temp,spp[30:0]}; prod=prod+spp; end end else c=3'bxxx; end //////////////// default: out= prod; endcase end end endmodule |
sir i want code for radix 8
Do you have the verilog codes for radix 8?
sir do you have the test bench for radix 4 code
do you have the tset bench of this radix 4 code
sir can you provide test bench of it..
I tried this but the product is always 0. Here is the test bench
`timescale 1 ns/10 ps
module mult_tb;
reg clock, reset ;
reg [15:0] multiplicand;
reg [15:0] multiplier;
reg [31:0] product;
reg [3:0] ready;
reg start;
multiplier dut(.clk(clock),.reset(reset), .x(multiplicand),.y(multiplier), .out(product));
initial begin
clock = 1’b0;
reset = 1’b0;
multiplicand = 16’b0000000000000000;
multiplier = 16’b0000000000000000;
product = 32’b00000000000000000000000000000000;
end
always #5 clock = ~clock;
initial
begin
reset = 1’b1;
clock = 1’b1;
ready = 1’b1;
start = 1’b1;
#3
multiplicand = 16’b0000000000001101;
multiplier = 16’b0000000000001111;
# 200;
$stop;
end
endmodule