16 bit Radix 4 Booth Multiplier Verilog Code

16 bit Radix 4 Booth Multiplier Verilog Code

Here we are sharing the verilog implementation of 16 bit radix 4 booth multiplier using sequential logic. It takes 16 clock cycle to multiply two 16-bit signed numbers.

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vaibhav
vaibhav
4 years ago

sir i want code for radix 8

Muhamad Firdaus bin Hasnan
Muhamad Firdaus bin Hasnan
4 years ago
Reply to  vaibhav

Do you have the verilog codes for radix 8?

asif siddiqui
asif siddiqui
3 years ago

sir do you have the test bench for radix 4 code

asif siddiqui
asif siddiqui
3 years ago
Reply to  vaibhav

do you have the tset bench of this radix 4 code

asif siddiqui
asif siddiqui
3 years ago

sir can you provide test bench of it..

Mohamed Eljahmi
Mohamed Eljahmi
1 year ago

I tried this but the product is always 0. Here is the test bench

`timescale 1 ns/10 ps

module mult_tb;

   reg clock, reset ;
   reg [15:0] multiplicand;
   reg [15:0] multiplier;
   reg [31:0] product;
   reg [3:0] ready;
   reg start;

   multiplier dut(.clk(clock),.reset(reset), .x(multiplicand),.y(multiplier), .out(product));

   initial begin
   clock     = 1’b0;
       reset     = 1’b0;
       multiplicand = 16’b0000000000000000;
   multiplier  = 16’b0000000000000000;
   product = 32’b00000000000000000000000000000000;
   end

   always #5 clock = ~clock;
   initial
   begin
   reset = 1’b1;
   clock = 1’b1;
   ready = 1’b1;
   start = 1’b1;
   #3
       multiplicand = 16’b0000000000001101;
       multiplier = 16’b0000000000001111;

       # 200;

       $stop;
   end
endmodule