What is Logic Equivalence Check | Formal Verification in VLSI

What is Logic Equivalence Check


Logic equivalence check or popularly known as LEC is one of the most important parts of ASIC VLSI Design. LEC check is a signoff check and if it is failing ( No Equivalence present) one cant’ tapeout.

While designing a VLSI chip, there are lot of changes that the design goes through. The changes may be very simple or complex. We know that, in VLSI, we do functional simulation to check where the chip or design is behaving as per functional specification. As the chip design or chip database changes multiple time during chip design cycle, it becomes very hard to verify the design functionality by simulation.

To solve this issue, there comes a new verification method which is called logic equivalence check or formal verification. LEC check makes sure the design is equivalent ( logically) even without running functional verification.  This saves lot of time and also helps immensely during RTL to GDSII implementation of ASIC.

LEC or FV is based on very simple principle of digital logic equivalence. It compares two digital logic and tells whether both are equivalent.

EDA Tools used in VLSI Industry for  Logic Equivalence Check

  1. Cadence Conformal
  2. Synopsys Formality

The below Youtube video provides in depth understanding about logic equivalence check or LEC check or FV check.

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