Pipeline Adder Verilog Code | Verilog Implementation of 16 Bit Pipeline Adder

Pipeline Adder Verilog Code

16 bit Pipeline  Adder Verilog Code

A pipeline adder is a one of the fast adder using the principle of pipelining.  This is a sequential adder, unlike combinational adders like Ripple Carry Adder, Carry Skip AdderCarry Look-ahead Adder etc needs a storage element and clock.

The general block diagram of a Pipeline Adder is shown below.

pipeline adder strucutre

 

To implement this in verilog we used  4-bit Carry Select Adder Slice as adder slice in verilog implementation of pipeline adder. The verilog code of 16 bit pipeline adder is given below.

The Verilog Code of 16-bit Pipeline Adder:

 

Pipelined Adder Simulation Result

Pipelined Simulation Result

 

Pipeline Adder Testbench Result

 

Cadence RTL compiler is used to synthesize the verilog  code with Uofu standard library.  We got the following schematic after mapping the hdl code to the standard library. This is basically the synthesized view.

 

RTL Complied Pipelined Adder

 

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