INTERVIEW QUESTIONS STANDARD CELL DESIGN
INTERVIEW QUESTIONS LIBRARY DESIGN
In this post we are providing some typical interview questions asked when you are looking giving interview for standard cell design position or library design engineer position or related job profile targeting standard cell related job profile.
These questions are mainly asked to freshers (NCGs) or 1-2 years of experience candidates who are going to start their journey in Standard Cell Design field.
- Draw Inverter Voltage Transfer Characteristics and clearly mention all the regions with details.
- What do you mean by delay? (Give Definition)
- Why do we take 50% of input while measuring delay?
- What are different power in CMOS circuit?
- What are the different components of Leakage current?
- What is short circuit current?
- Does leakage current flow when transistor is on?
- What is the difference between a latch and a flipflop?
- Draw 2:1 MUX using logic gate.
- How can you draw a flipflop using MUX?
- Calculate setup and hold time of the circuit above.
- Why slew is defined for 20%-80% or 10%-90 %?
- Mention all the factors that affect the delay of a circuit.
- Let’s consider the below situation where S means slew and C means capacitor.
For which combination of slew and capacitor you will get (i) maximum delay (ii) minimum delay
- How do slew and capacitor affects the power as per above question?
- How do power calculation tools such as PT-PX calculates power of VLSI circuit?
- Can propagation delay be negative?
- What is functionality of the below circuit?
Ans: Tristate Buffer.Here, B input is the control input of the tri-state buffer. When B=0, it acts like a simple buffer. If B=1, both NMOS and PMOS is off irrespective of A value. Now, if B=0, both the PMOS and NMOS gate inputs gate A’. So, it’s like A’ is fed to an inverter whose ouput is simply A.
If you draw the truth table it will be something like below.
If you have any questions regarding the above, please comment below.