16 bit Carry Skip Adder Verilog Code | Carry Bypass Adder Verilog Code

Carry Skip Adder Verilog Code

16 bit Carry Bypass Adder Verilog Code

carry-skip adder (also known as a carry-bypass adder) is an adder implementation that improves on the delay of a ripple-carry adder with little effort compared to other adders. The improvement of the worst-case delay is achieved by using several carry-skip adders to form a block-carry-skip adder. For more information about carry bypass adder you can refer to this wikipedia article.

Basic structure of 4-bit Carry Skip/Bypass Adder is shown below.



The Verilog Code for 16-bit Carry Skip Adder is given below-



Carry Skip Adder Simulation Results:




Cadence RTL compiler is used to synthesize the Carry Skip Adder verilog  code with Uofu standard library.  We got the following schematic after mapping the hdl code to the standard library. This is basically the synthesized view.

16 Bit Module

carry skip 16 bit


4-bit Module:




2X1 MUX Module:



If you have any query/suggestion please feel free to comment below the post.

0 0 vote
Article Rating
Notify of
1 Comment
Newest Most Voted
Inline Feedbacks
View all comments
Adhiraj Sehgal
Adhiraj Sehgal
1 year ago

Can you please provide the test bench as well for Xilinx.