16 bit Ripple Carry Adder Verilog Code

Ripple Carry Adder Verilog Code

N- bit Ripple Carry Adder Verilog Code

Ripple carry adder is the basic adder architecture.  In ripple carry adder the carry bit may  ripple from first bit to last bit. Hence we call it  ‘Ripple Carry Adder’ . The general structure of 4-bit ripple carry adder is shown below.

ripple carry adder

Here we can see the LSB bits are A0, B0 and C0 where C0 is the input carry bit.  Output of 1-bit full adder is S0 and C1.

where S0= LSB sum bit   and C1=Carry Out of first 1-bit full adder

The boolean equation for 1 bit full adder output, S0 and C1, is given  by

S0=A0⊕B0⊕C0  and   C1= (A0⊕B0).C0 + A0B0.

A 4-bit Ripple Carry adder is built by  cascading four 1-bit full adders in series.  The out  carry bit of every full adder is fed to the input of the next full adder.

Now as we have 4-bit ripple carry adder so it can further be cascaded in series to get higher bit adder.

For example, we can get 16 -bit Ripple Carry Adder by cascading in series four 4-bit ripple carry adders. While writing the verilog code for 16-bit Ripple carry adder the same procedure is used. First the verilog code for 1-bit full adder is written. From this, we can get the 4-bit ripple carry adder.  Now,by using  this 4-bit ripple carry adder  16-bit ripple carry adder verilog code has been written.

Similar way, we can get N-bit ripple carry adder.

The Verilog Code for 16-bit Ripple  Carry is given below-

 

 

We are here providing the testbench for 16-bit Ripple Carry Adder

 

16 bit Ripple Carry Adder Simulation Results:

ripple_carry_simulation

 

Also the monitor command result is –

ripple_carrry

Cadence RTL compiler is used to synthesize the verilog  code with Uofu standard library.  We got the following schematic after mapping the hdl code to the standard library. This is basically the synthesized view.

sythesized_view

 

If you have any query/suggestion please feel free to comment below the post.

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